Electrically erasable and programmable memory devices having arrays of what are known as flash memory cells are found in a wide variety of electrical devices. A flash cell, also called a floating gate transistor memory cell, is similar to a field effect transistor, having a channel region between a source and a drain and a control gate over the channel region. In addition the flash cell has a floating gate between the control gate and the channel region. The floating gate is separated from the channel region by a layer of gate oxide, and an interpoly dielectric layer separates the control gate from the floating gate. Both the control gate and the floating gate are formed of doped polysilicon. The floating gate remains floating or electrically isolated. A flash cell is programmed by applying appropriate voltages to the control gate, the drain, and the source, causing electrons to pass from the channel region to the floating gate through the gate oxide. The voltage applied to the control gate, called a programming voltage, determines the amount of charge residing on the floating gate after programming, and the charge determines the voltage that must be applied to the control gate in order to allow the flash cell to conduct current between the source and the drain. This voltage is termed the threshold voltage of the flash cell, and is the physical form of the data stored in the flash cell. As charge is added to the floating gate the threshold voltage of the flash cell increases.
Those of ordinary skill in the art will appreciate that a read operation from a flash memory device can be considered to comprise two sequential stages. The first stage is a latch stage where the voltage level stored in the flash cell is sensed by sense amplifiers and latched into a buffer. The second stage is an output stage where the data latched in the buffer is output to the data output (DQ) pins of the device. With conventional flash memory architectures, the latch stage of a read operation involves sensing the state of an entire row of memory locations and latching the sensed values in a latch. This occurs in response to assertion of a “READ” signal. The data is available at the memory device's output pins some time after the READ signal has been asserted.
The earliest flash memory devices were primarily asynchronous devices, meaning that no external clocking signal was required for their operation. The primary significant timing constraint for an asynchronous flash memory is a latency period following assertion of the READ command before the data was available at the output (DQ) pins.
Later, synchronous flash memories were introduced. A synchronous flash memory operates (or appears from external to the device to operate) in essentially the same manner as a conventional synchronous dynamic access memory (SDRAM). Data is read from a synchronous flash memory by first asserting a row address strobe (RAS) signal to latch in a row address applied to the address inputs of the device, and subsequently asserting a column address strobe (CAS) signal to latch in a column address of the memory location to be accessed. Both RAS and CAS are asserted in a specified timed relationship with a clock signal (CLK) defining the operational speed of the memory device. A latency period following assertion of the CAS signal, measured in terms of some number of clock cycles, must elapse before valid data stored at the addressed location is available at the device's DQ output pins.
Examples of synchronous flash memory devices such as described generally above include the SynchFlash® family of synchronous flash memory devices commercially available from Micron Technology, Inc., Boise, Id. (the Assignee of the present invention). Memories in the SynchFlash® family feature SDRAM-compatible interfaces (pinouts) and timing specifications. Synchronous flash memory architectures are also disclosed in detail in U.S. Pat. No. 6,314,049 to Roohparvar, entitled “Elimination of Precharge Operation in Synchronous Flash Memory,” and in U.S. Pat. No. 6,327,202 to Roohparvar, entitled “Bit Line Pre-Charge in a Memory.” The aforementioned '049 and '202 patents are commonly assigned to the Assignee of the present invention and are hereby incorporated by reference herein in their respective entireties.
As an improvement over conventional flash memories, it has been proposed in the prior art to utilize multi-bit flash memory cells (alternatively referred to as multi-level or multi-state flash cells) in a flash memory to improve the capacity of the memory and the speed with which data can be read from and written to the memory. A multi-bit or multi-state flash cell is a flash memory cell for which multiple, distinct threshold voltage levels are defined over a voltage range within the flash cell. Each distinct threshold voltage level corresponds to a set of data bits, with the number of bits representing the amount of data which can be stored in the multi-state flash cell. This method allows multiple bits of binary data to be stored within a single flash cell. When reading the state of the flash cell, the threshold voltage level for which the flash cell conducts current corresponds to a bit set representing data programmed into the flash cell.
A multi-state flash cell is programmed by applying a programming voltage to the control gate and holding the drain to a constant voltage over a proper time period to store enough charge in the floating gate to move the threshold voltage of the flash cell to a desired level. This threshold voltage level represents a state of the flash cell corresponding to the data (bit set) stored in the flash cell.
An example of a prior art flash memory device having multi-state memory cells is disclosed in U.S. Pat. No. 6,209,113 to Roohparvar, entitled “Method and Apparatus for Performing Error Correction on Data Read from a Multistate Memory.” The '113 patent is commonly assigned to the Assignee of the present invention and is hereby incorporated herein by reference in its entirety.
Those of ordinary skill in the art will appreciate that for a multi-state memory cell, the latch stage of a read cycle is inherently slower compared with single-bit flash memory cells, due mainly to the time that is required to “resolve” the voltage on each cell. (Those of ordinary skill in the art will understand that to “resolve” the voltage on a flash memory cell involves sensing the voltage stored in the cell and translating that voltage into one of a plurality of bit-sets defined for that cell.) That is, a higher resolution of sensing is required to distinguish between the multiple logic levels, thus requiring more sensing time as compared with single-bit flash memory cells. Often, two separate sense amplifiers are involved in resolving the voltage level stored in a multi-level cell. However, once the latching stage is complete for an addressed row of cells, the outputting stage of a read operation is essentially the same for 1 bit-per-cell as for 2 (or more) bits-per-cell.
FIG. 1a illustrates the cell data map for a conventional one-bit-per-cell flash memory cell. As shown in FIG. 1a, two separate levels or ranges are defined within the overall flash cell Vthreshold range. When reading from such a flash cell, all that is necessary is to determine whether the threshold voltage is above or below the midpoint between the two levels. Voltages in one level are interpreted as a single binary bit (zero or one) while voltages in the other level are interpreted as the complementary binary bit (one or zero).
FIG. 1b on the other hand illustrates the cell data map for a multi-level flash memory cell capable of storing two bits. As can be seen in FIG. 1b, the data map defines four separate ranges or levels (Levels 0, 1, 2, and 3) within the range of the cell's overall maximum Vthreshold. Each level is assigned a two-bit pair or bit-set, 0,0, 0,1, 1,0, or 1,1. The advantages of such multi-level cells are well known and appreciated by those of ordinary skill in the art. The perceived disadvantage of multi-level cells is that the time to resolve the correct voltage level is generally longer than for conventional flash memory cells. One possible approach to sensing a multi-level cell such as represented by the map of FIG. 1b is to first sense whether the threshold voltage is above or below the boundary between Level 1 and Level 2, and next ascertain whether the threshold voltage is above or below the boundary between Level 0 and Level 1 or between Level 2 and Level 3 (depending upon the outcome of the first sensing phase). In implementation, such an approach can require two sense amplifiers per cell, and the overall sensing process can take substantially longer than for sensing a conventional flash cell. (The sensing process for multi-level cells can possibly be accelerated at the expense of sensing accuracy; however, this can necessitate additional error correction circuitry for the memory.)